The present invention relates to a semiconductor device having a fin-shaped channel portion, and a method of fabricating the same.
Shrink is required for insulated gate field-effect transistors in order to prevent a chip size from increasing along with high integration of semiconductor devices.
Cut-off characteristics of a drain current becomes worse because the drain current becomes unable to be controlled any more by a gate voltage due to a short channel effect as a gate length is shortened to make a source region and a drain region close to each other.
Therefore, even when a gate is closed, a leakage current is caused to flow between the source region and the drain region because silicon is a semiconductor having a relatively high electric conductivity. That is to say, a phenomenon called punch-through occurs. A double-gate structured field effect transistor in which not only an upper surface of a channel portion, but also a lower surface thereof is held between opposite portions of a gate electrode, thereby making it possible to perfectly control a channel by a gate voltage applied to the gate electrode is effective in suppression of the punch-through.
It is difficult to form a gate electrode on a lower surface of a channel portion in accordance with a conventional method of putting materials one on top of another, thereby fabricating an insulating gate field-effect transistor. In order to solve this problem, there is known a double-gate structured field effect transistor structured such that a channel portion is stood vertically to a surface of a substrate, and both sides of a fin-shaped channel portion is held between opposite portions of a gate electrode (hereinafter referred to as “a FINFET”). The FINFET, for example, is disclosed in a non-patent literary document of 2005 Symposium on VLSI Technology Digest of Technical Papers 11A-1, pp. 194 and 195.
For fabrication of the semiconductor device disclosed in the non-patent literary document, a silicon layer is recess-etched in order to form a source region and a drain region of a FINFET, thereby leaving a part of the silicon layer, and a silicon germanium layer is epitaxially grown on the part of the silicon layer thus left. A compressive stress is generated in a channel portion by the silicon germanium layer to give the channel portion a strain, thereby increasing a mobility of carriers.
However, the semiconductor device disclosed in the non-patent literary document involves such a problem that a dispersion necessarily occurs in a thickness of the remaining silicon layer because there is no etching stopper in the phase of the recess etching.
As a result, there is encountered such a problem that a total amount of silicon germanium layer disperses in correspondence to the thickness of the remaining silicon layer, so that the magnitude of the compressive stress generated in the channel portion fluctuates, and thus the mobility of the carriers in the channel portion necessarily disperses.
Moreover, there is caused such a problem that the lower portion of the channel portion contacts no silicon germanium layer because the remaining silicon layer underlies each of the source region and the drain region, which results in that an amount of strain in the lower portion of the channel portion decreases, thereby reducing the mobility of the carriers in the lower portion of the channel portion.